## FPGA Implementation and Evaluation of a Genetic Algorithm for Digital Adaptive Nulling using Space-Time Adaptive Processing.

##### Master thesis

##### Permanent lenke

http://hdl.handle.net/11250/2371478##### Utgivelsesdato

2015##### Metadata

Vis full innførsel##### Samlinger

##### Sammendrag

By using multiple antennas it is possible to do beam forming of signal reception. Each antenna signal is scaled and delayed before they are added together. By scaling and delaying the signals from various antennas differently, the reception beam form is changed. This scaling and delaying can be done by multiplying each antenna signal with a complex number, this complex number is called a weight in this thesis.
Adaptive nulling means dynamically changing the weights to avoid signal reception from undesired directions based on the received signal. When receiving GPS signals, the desired signals power level is usually lower than the noise floor. If one assumes that there are enough GPS satellites, one can improve the SNR by finding power minimizing weights. This is equivalent to trying to remove all signal reception from directions of powerful signals. The optimal Wiener solution can be found by the direct matrix inversion, DMI, method. The DMI method is complex and large parts of the method can not be done in parallel. The goal of this thesis is to determine whether an FPGA implementation of the genetic algorithm, an iterative random search algorithm, realistically can replace the DMI method. The target FPGA in this thesis is Xilinx Virtex 6 XC6VLX195T.
A MATLAB model of the genetic algorithm is developed. This model together with some assumptions is used to find reasonable parameters for the genetic algorithm. The resulting algorithm is implemented in VHDL. The VHDL implementation is partially tested, synthesised and run through place and route. The genetic algorithm module is supposed to be part of a bigger FPGA design. The amount of inputs and outputs in the genetic algorithm module makes it impossible to route the design by itself on the target FPGA. The design is wrapped to solve this problem. The maximum clock frequency of the wrapped design is 180 MHz after place and route.
It turns out that the weights found by the genetic algorithm is far from the optimal Wiener solution, which is the theoretically best weights that can be found. It does not seem likely that the genetic algorithm can compete with the DMI algorithm in this real time scenario. The achieved performance of the genetic algorithm is a received power reduction of around 20 dB. When using the DMI method the power reduction is 50-60 dB. Although it has been shown that the performance tests of both the genetic algorithm and the DMI method were not ideal, there is a major performance difference. The genetic algorithm finds new weights faster than the DMI method. However the gap between the two methods in quality of the weights is presumed too large to be closed.