Applying a Digital Verification Approach to an Analog Protocol - Further development of a reusable verification component based on the Universal Verification Methodology

Abstract

Analog and mixed-signal circuit designs are more important now than ever, due to the popularity of wearable and wireless electronic devices. The forecast of the Internet of Things (IoT) suggest that the need for advanced Mixed-Signal System-on-Chips (MSSoC) will be present in many years to come. The increasing functionality required by the analog parts of MSSoCs presents a great challenge in the verification of such systems. Simulation Program with Integrated Circuit Emphasis (SPICE) tools are still the main technique used to verify analog circuits. However, the speed of SPICE simulation becomes an issue with the increasing complexity of analog designs. Other verification strategies are necessary in order to reach sufficient functional verification within the time to market. Real Value Modeling (RVM) is a technique that can be used for digital simulation of analog circuit, yielding a greater speed performance than SPICE tools. By exploiting RVM in combination with the de facto standard for digital verification, the Universal Verification Methodology (UVM), sufficient functional coverage can be achieved.

This thesis presents the design and implementation of a UVM based Universal Verification Component (UVC) for the Near Field Communication (NFC) protocol. The final UVC enables protocol verification of NFC devices using the NFC-A technology. By leveraging Metric Driven Verification (MDV) and RVM models, the UVC achieves digital simulation speed in functional verification. A mathematical model for driving stimulus on an analog interface is presented as well as a model for estimating the frequency of the observed interface. The models enable driving and monitoring of analog characteristics such as amplitude, modulation and frequency.

Verification was performed by the UVC in a testbench with a Device Under Test (DUT) using the NFC-A technology. 100\% functional coverage was reached at digital simulation speeds, according to a verification plan. Visual inspection of the driven and monitored interface confirms the UVCs ability to perform correct protocol verification. The results indicate that the UVC can mitigate the speed performance of SPICE simulation to improve functional verification of analog modules.