Modeling a Two Stage SAR-Assisted Pipeline ADC
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In this work, the 15-bit SAR-assisted pipeline ADC has been examined, and high-levelmodels have been made in Cadence to verify its operation. The goal is to achieve a resolutionof more than 14 ENOB at a sampling frequency of 32 MHz. Specifications for thevarious sub-blocks have been derived based on general circuit design theory and previouswork in the field, and the models have been implemented accordingly. Using an amplifiergain of 84.34 dB, the model achieves an ENOB of 14.43 with input frequencies 218.75 Hzand 15MHz, using a sample frequency of 32 MHz.