| dc.description.abstract | In this work, the 15-bit SAR-assisted pipeline ADC has been examined, and high-level
models have been made in Cadence to verify its operation. The goal is to achieve a resolution
of more than 14 ENOB at a sampling frequency of 32 MHz. Specifications for the
various sub-blocks have been derived based on general circuit design theory and previous
work in the field, and the models have been implemented accordingly. Using an amplifier
gain of 84.34 dB, the model achieves an ENOB of 14.43 with input frequencies 218.75 Hz
and 15MHz, using a sample frequency of 32 MHz. | |
