DPA-Resistant ASIC implementation of AES
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With the increased proliferation of small embedded systems connected to theinternet and the internet-of-things, the security concerns becomes increasinglyimportant. Encryption, and the protection of encrypted circuits can be of greatimportance. With this thesis the aim was to design an encryption chip thatwas able to operate without leaking sensitive information even in the presenceof a malicious adversary, specifically to be able to withstand differential poweranalysis attacks.A masked 128-bit data-path AES encryption and decryption architecture isproposed, supporting AES-128, 192 and 256 using cipher-block chaining modeof operation. Synthesized to 65nm technology, the system achieves a keymode-dependent throughput of 0.99-1.32 Gb/s operating at 400MHz with an averagepower consumption of 167.9mW. Our masking approach should withstand secondorder DPA-attacks at an area cost of 486% compared to the unmasked equivalentcircuit.