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DPA-Resistant ASIC implementation of AES

Fegran, Henrik
Master thesis
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13145_FULLTEXT.pdf (983.1Kb)
13145_ATTACHMENT.zip (1.855Mb)
13145_COVER.pdf (234.4Kb)
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http://hdl.handle.net/11250/2371531
Utgivelsesdato
2015
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  • Institutt for elektroniske systemer [1526]
Sammendrag
With the increased proliferation of small embedded systems connected to the

internet and the internet-of-things, the security concerns becomes increasingly

important. Encryption, and the protection of encrypted circuits can be of great

importance. With this thesis the aim was to design an encryption chip that

was able to operate without leaking sensitive information even in the presence

of a malicious adversary, specifically to be able to withstand differential power

analysis attacks.

A masked 128-bit data-path AES encryption and decryption architecture is

proposed, supporting AES-128, 192 and 256 using cipher-block chaining mode

of operation. Synthesized to 65nm technology, the system achieves a keymode-

dependent throughput of 0.99-1.32 Gb/s operating at 400MHz with an average

power consumption of 167.9mW. Our masking approach should withstand second

order DPA-attacks at an area cost of 486% compared to the unmasked equivalent

circuit.
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