Browsing NTNU Open by Author "Aunet, Snorre"
Now showing items 1-20 of 70
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4-7GHz Tunable Programmable Pulse Generator in 65nm CMOS
L'Orange, Simon (Master thesis, 2017)A pulse counter has been designed and simulated in a standard 65nm process technology in schematic and can be implemented in a pulse generator. The maximum values from the schematic shows a frequency of 12.5GHz and a power ... -
A comparative study for commercial TVOC sensors
Paintsil, Wesley Ryan (Master thesis, 2019)Inneklima har blitt viktigere med årene da menneskelig aktivitet i økende grad skjer innendørs. Internet of tings har gjort det mulig for mennesker å sammhandle bedre med den fysiske verden ved å hente informasjon ved hjelp ... -
A loadless 6T SRAM cell for sub- & near- threshold operation implementedin 28 nm FD-SOI CMOS technology
Låte, Even; Ytterdal, Trond; Aunet, Snorre (Journal article; Peer reviewed, 2018)Most ultra low power SRAM cells operating in the sub and near threshold region deploy 8 or more transistors per storage cell to ensure stability. In this paper we propose and design a low voltage, differential write, single ... -
A Sub-100mV Supply Voltage Standard-Cell Based Memory in 22nm FD-SOI
Sæther, Harald (Master thesis, 2022)Ønsket om reduksjon i strømforbruk har motivert design av integrerte kretser som opererer i sub-terskel domenet. Kretser som opererer ved sub-terskel forsyningsspenninger trenger robuste arkitekturer og teknikker, som tåler ... -
An Ultra-Low Voltage and Low-Energy Level Shifter in 28 nm UTBB-FDSOI
Vatanjou, Ali Asghar; Ytterdal, Trond; Aunet, Snorre (Journal article; Peer reviewed, 2018)Abstract—A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used ... -
Analysis and Visualisation of Clock Tree Power in a full-chip-design
Ro, Hans Jørgen Myrvang (Master thesis, 2014)In this thesis a tool to graph power density in a chip by combining placement data with power estimation results has been made for Nordic Semiconductor. The goal was to utilize the data generation power of the power ... -
Applying Asynchronous Completion Detection to the AVS Domain
Gausdal, Kaja (Master thesis, 2020) -
Automated Desynchronization Using Pyverilog
Rotevatn, Synnøve Andersen (Master thesis, 2021) -
Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping
Låte, Even; Ytterdal, Trond; Aunet, Snorre (Peer reviewed; Journal article, 2020)This brief presents an approach that dynamically exploits content dependencies in asymmetric memory cells. By using a capacitive, logic-value majority circuit and an extra column of memory cells, words are conditionally ... -
Channel Filter Cross-Layer Optimization
Talstad, Joar Nikolai (Master thesis, 2015)The recent raise of Internet of Things has increased the demand of energy-efficient wireless devices. However, the design process of a low-energy, high-performance device for all operational cases is not trivial. Thus, in ... -
Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology
Hossein Zadeh, Somayeh; Ytterdal, Trond; Aunet, Snorre (Chapter, 2018)Five ultra low voltage and low power full adders have been designed and analyzed with CMOS logic structure. To compare these adders, different metrics including worst case delay, average power, PDP, and PDP*Leakage have ... -
Design and Implementation of a Digital Standard Cell Library for 28 nm Technology
Steinsland, Christian (Master thesis, 2021)A digital standard cell library has been designed and implemented for a 28 nm technology. The library has been designed and optimized for a supply voltage of 300 mV, to be compatible with a standard design flow. Each cell ... -
Design and Implementation of a Magnetic Energy Harvesting System for Low Primary Current Applications
Skavnes, Solveig (Master thesis, 2021)Energihausting er å utnytte små mengder omkringliggjande energi for å drive eit lavenergisystem, slik som for eksempel ei sensornode. Dette kan gjerast frå magnetfelta som kjem frå ein vekselstraum, Ip, som går gjennom ei ... -
Design of a near-threshold Microcontroller
Oma, Åsmund Kvam (Master thesis, 2016)There is a strong interest in ultra low voltage digital design as emerging applications like Internet of Things, wearable biomedical sensors, radio frequency identification, sensor networks and more are gaining traction. ... -
Design of an ASIC Evaluation Kit - Conceptualization, schematic design, PCB layout and preliminary testing of a mixed-signal board
Fredriksen, Arne Olav G (Master thesis, 2015)The development of an upcoming ASIC by the company IDEAS calls for the design of an accompanying evaluation kit so that it may be accessible for testing in a laboratory setting. In addition to supporting the ASIC in question, ... -
Design of low-power consumption adder: High speed and short delay
Zhou, Qingrui (Master thesis, 2013)The mission will provide a good explanation of ultra-low and high-speed adder. It started with a brief introduction of simple adder. The assignment will provide an introduction of key performance of the ultra-low and ... -
Design of SRAM for Sub-100mV Operation Using 22 nm FD-SOI
Skirbekk, Asta (Master thesis, 2023)Energihøsting er en lovende løsning for tingenes internett (IoT), siden dette fjerner behovet for hyppig bytting av batterier. Mange energihøstingsmetoder strever med å lage høye forsyningsspenninger, og dette er et problem ... -
En Konfigurerbar og Fleksibel Arkitektur for Laveffekt, Energieffektiv Maskinvareakselerasjon av Nevrale Nettverk basert på Foldning
Christensen, Steinar Thune (Master thesis, 2019)Nevrale nettverk basert på foldning (CNNs) har blitt essensielle i dagens Kunstig-Intelligensog Maskinlærings-anvendelser. Dette gjelder særlig bildegjenkjenning. Denne masteroppgaven presenterer en konfigurerbar, allsidig ... -
An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V
Låte, Even; Ytterdal, Trond; Aunet, Snorre (Peer reviewed; Journal article, 2020)We propose architectural advances in low voltage, energy efficient, level shifters. A write assist circuit is introduced,to support up-conversion of deep subthreshold inputs. We also present an approach to reduce the leakage ... -
Energy Efficient Subthreshold Digital Building Blocks
Hossein Zadeh, Somayeh (Doctoral theses at NTNU;2022:141, Doctoral thesis, 2022)Many IoT applications such as implantable biomedical devices, sensor nodes in the internet of things operate in the kHz range, and power consumption is the primary concern in such applications. However, the required voltage ...