Energy Efficient Subthreshold Digital Building Blocks
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Many IoT applications such as implantable biomedical devices, sensor nodes in the internet of things operate in the kHz range, and power consumption is the primary concern in such applications. However, the required voltage of the most implantable electronic devices is 2-3 V . The output properties of the most recent in vivo energy harvesters (IVEHs) is 150 mV and below [47, 61] which could suit the low voltages for the subthreshold circuits, while saving energy by not having to use as energy costly DC-DC conversion as one would for higher supply voltages. Therefore, subthreshold circuits operating at the supply voltages lower than the absolute value of the threshold voltage of the transistors might be the best option for such applications. The power consumption is reduced as the circuit supply voltage is lowered down towards and below the threshold voltage of the transistors, but it will increase the propagation delays. It may not be a concern for low to medium performance. Voltage scaling in integrated circuits brings challenges for a designer that has to be considered during the design phase. The impact of the process, voltage, and temperature variations increases by voltage scaling and affects the functionality of the circuits. This thesis focuses on designing and exploring energy efficient computing and memory circuits at ultra low voltage subthreshold regime at the different abstraction levels. Techniques such as body biasing (reverse body bias), transistor stacking, device sizing, multi-threshold voltage devices at the gate level have been explored to reduce the power consumption especially static power, taking into account the reliability issue and process, voltage and temperate variations. At the circuit level, different topologies of the full adders based on the standard CMOS designed for subthreshold supply voltages have been compared considering the functionality and reliability issues. In addition, an optimal back gate bias has been proposed in a commercially available 22 nm FDSOI (Fully Depleted Silicon On Insulator) technology that minimizes the energy per operation consumption of subthreshold digital CMOS circuits and improves the reliability. The adder as a case study under optimal body bias consumes 4.6 percent less energy than zero body bias at Vdd=150 mV and a frequency of 1 kHz. At the architectural level, two different types of adders including Kogge Stone adder (KSA), the fastest adder, and the Ripple Carry adder (RCA), the simplest adder have been designed and fabricated for supply voltages as low as Vdd = 140 mV. The adders have been synthesized at the gate level using full custom standard cell library designed for ultra low voltage subthreshold regime. The gap between simulation and measurement results is filled with successful implementation and comparison of the ultra low subthreshold adders at such a low voltage 140 mV. To the best of the authors knowledge this is the first measurement comparison between two different adder architectures for ultra low supply voltages as low as 140 mV. Simulated results in  indicated that the RCA is 1.36X energy efficient compared to the KSA at the same speed. Measured results presented here, show that the RCA is 4.15X to 1.92X energy efficient compared to the KSA at supply voltages between 250 to 500 mV. In addition, the RCA designed in this study outperforms the reported works in terms of a defined FoM which is (Tech)=(Vmin:Energymin). Digital circuits designed for applications like sensor networks, implantable biomedical devices and environmental monitoring need to work at different conditions. For example, the temperature range that circuit should work. In this thesis, we have studied the performance of the circuits at different temperatures, supply voltage and in the presence of mismatch and process variations. The multiple threshold voltage technique has been used to design a 7T loadless SRAM cell for subthreshold regime, and demonstrate the different trade offs for single, regular and flip well types SRAM memories. Among all devices used (HVT, RVT, LVT and, SLVT) available in a commercially available 22 nm FDSOI technology, the best combination for minimizing energy per access is HVT devices as the driver transistors and RVT for the rest of the transistors. The single well SRAM has the lowest leakage per bit cell over its regular and flip well counterparts. The regular well type has lower static noise margin (SNM) variability. An 8-bit RCA has been designed by using multiple threshold voltage technique in 22 nm FDSOI technology. The simulation results based on the extracted netlist from layout show that the energy per one bit addition is lowest in our adder compared to the proposed adders in FDSOI technology. The energy per one bit addition for the proposed adder at Vdd = 300 mV is 0.23 fJ. We have also used the dynamic body bias technique for the adder to balance the PUN/PDN (Pull up/Pull down networks). The results show that the adder with dynamic body bias is robust and functional at the supply voltage 60 mV lower that that of the adder with conventional body bias. Additionally, a new standard cell memory based on the NAND race free D-latch has been synthesized and explored. The simulation results show that using robust NAND race free D-latch leads to lower minimum operating supply voltage, and hence, lower power and energy for standard cell memory. This dissertation analyzes subthreshold digital circuits using 22 nm siliconon-insulator process and 130 nm bulk CMOS technology. We also fabricated and tested the digital circuits in 130 nm technology and the measurement results are compatible with the simulation results.
Has partsPaper 1: Hossein Zadeh, Somayeh; Ytterdal, Trond; Aunet, Snorre. Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology. I: Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE 2018 ISBN 978-1-5386-7656-1. s. -
Paper 2: Hossein Zadeh, Somayeh; Ytterdal, Trond; Aunet, Snorre. Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder. I: 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE 2019 ISBN 9781728127699. s. -
Paper 3: Hossein Zadeh, Somayeh; Ytterdal, Trond; Aunet, Snorre. Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology. I: 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE 2019 ISBN 9781728127699. s. -
Paper 4: Hossein Zadeh, Somayeh; Ytterdal, Trond; Aunet, Snorre. An ultra low voltage subthreshold standard cell based memories for IoT applications. I: Proceedings, 28th Iranian Conference on Electrical Engineering. IEEE conference proceedings 2020 ISBN 978-1-7281-7296-5. s.
Paper 5: Hossein Zadeh, Somayeh; Ytterdal, Trond; Aunet, Snorre. Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders. I: 2020 IEEE Nordic Circuits and Systems Conference (NorCAS). IEEE 2020 ISBN 978-1-7281-9226-0. s. -
Paper 6: Hossein Zadeh, Somayeh; Ytterdal, Trond; Aunet, Snorre. Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology. I: 2020 IEEE Nordic Circuits and Systems Conference (NorCAS). IEEE 2020 ISBN 978-1-7281-9226-0. s. -
Paper 7: Hossein Zadeh, Somayeh; Ytterdal, Trond; Aunet, Snorre. Subthreshold Power PC and Nand Race-Free Flip-Flops in Frequency Divider Applications. I: Proceedings, 2021 IEEE Nordic Circuits and Systems Conference (NORCAS). IEEE 2021 ISBN 978-1-6654-0712-0. s. -
Paper 8: Hossein Zadeh, Somayeh; Ytterdal, Trond; Aunet, Snorre. Subthreshold Energy Efficiency of Serial Versus Parallel Adders. This paper is submitted for publication and is therefore not included.