4-7GHz Tunable Programmable Pulse Generator in 65nm CMOS
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A pulse counter has been designed and simulated in a standard 65nm process technology in schematic and can be implemented in a pulse generator. The maximum values from the schematic shows a frequency of 12.5GHz and a power consumption of 2.749mW. PVT simulations at 12.5GHz work with a variation in voltage of $2.5$\% from a supply of 1V, a temperature variation over [-40,80] degrees and in the corners SS, SF, FS, TT and FF while meeting the specifications. This shows that it has the possibility to both be implemented in layout but also is a plausible solution to counting pulses to vary the bandwidth. It also has the possibility to work over a great range of frequencies. The synchronous counter in TSPC logic has been resimulated with addition circuitry. The addition circuitry is to make it possible to control the counter, buffers on the clock signal, control signal from a lower clock system and get the right amount of pulses out.