Blar i NTNU Open på forfatter "Ytterdal, Trond"
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Amplifier for optimal reflection Coefficient of ultrasound transducer: A study of op amp based circuits for ultrasound transducers, targeted for low reflection Coefficient, high gain, and low noise
Mainou Gomez, José Francisco (Master thesis, 2012)Reverberation is defined as equally-spaced, bright linear echoes resulting from reflection from specular-type interfaces. They are provoked by the acoustic Impedance change between the tissue and transducer front surface. ... -
An 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimation
Garvik, Harald; Wulff, Carsten; Ytterdal, Trond (Journal article; Peer reviewed, 2017)A noise-shaping SAR ADC implemented in 28 nm UTBB FDSOI is presented. A cascaded FIR-IIR loop filter topology is used, and implemented as an inverter-based switched-capacitor circuit. The loop filter also employs input ... -
An energy efficient noise-shaping SAR ADC in 28 nm FDSOI
Garvik, Harald (Master thesis, 2015)In a noise-shaping SAR ADC, oversampling and noise shaping are used to increase the conversion accuracy beyond that the SAR exhibits alone. To implement the noise shaping, the residue voltage present at the SAR DAC plates ... -
An Ultra-Low Power Analog-to-Digital Converter in 22 nm FD-SOI CMOS Technology
Haraldstad, Jostein; Nentwich, František (Master thesis, 2023)Suksessiv-approksimasjon-register (SAR) analog-til-digital omformer (ADC) er en energieffektiv arkitektur, kapabel av lavt strømforbruk eller høy presisjon samtidig som energieffektivitet (FoM) i verdensklasse oppnås. ... -
An Ultra-Low Power Analog-to-Digital Converter in 22 nm FD-SOI CMOS Technology
Haraldstad, Jostein; Nentwich, František (Master thesis, 2023)Suksessiv-approksimasjon-register (SAR) analog-til-digital omformer (ADC) er en energieffektiv arkitektur, kapabel av lavt strømforbruk eller høy presisjon samtidig som energieffektivitet (FoM) i verdensklasse oppnås. ... -
An Ultra-Low Power SAR-ADC in 65 nm CMOS Technology
Josephsen, Simon (Master thesis, 2013)This master?s thesis presents the design, implementation and layout of an ultra-low power 9-bit 1 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS technology. The proposed ADC ... -
An Ultra-Low Power SAR-ADC in 65 nm CMOS Technology
Josephsen, Simon (Master thesis, 2013)This master thesis presents the design, implementation and layout of an ultra-low power 9-bit 1 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS technology. The proposed ADC ... -
An Ultra-Low Voltage and Low-Energy Level Shifter in 28 nm UTBB-FDSOI
Vatanjou, Ali Asghar; Ytterdal, Trond; Aunet, Snorre (Journal article; Peer reviewed, 2018)Abstract—A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used ... -
Analyzing and improving graphics processing performance in microcontrollers
Nadig, Chinmayi Hassan Shyamprasad (Master thesis, 2020)A typical microcontroller unit (MCU) has limited capabilities for processing and displaying graphics, due to power and size constraints. An increasing demand for rich graphical user interface (GUI) applications in battery ... -
ASIC Implementation of a 16-Bit Asynchronous ALU for Ultrasound Application
Tawhid, Sanjida Orin (Master thesis, 2021)In this thesis, An Application-Specific Integrated Circuit(ASIC) implementation of a 16-bit low-power Arithmetic Logic Unit(ALU) for Ultrasound CPU is proposed. The proposed ALU design can perform Addition and Multiplication ... -
Batteriovervåking
Aarflot, Øystein Andreas (Master thesis, 2009)Denne rapporten begynner med å presentere de ulike batteritypene som har vært og er aktuelle å benytte i elbiler. Videre er de ulike kildene til feil vurdert. Måleparametere og vanlige metoder for å korrigere avvik og sikre ... -
Behavioral Modelling and Design of Noise Shaping SAR ADC in 22nm FDSOI
Balasubramanian, Shankkar (Master thesis, 2019)Successive Approximation Registers(SAR) Analog to Digital Converters(ADCs) are very power efficient for Effective Number Of Bits(ENOB) below 9 bits. Above 9 bits, low noise comparator current could potentially limit the ... -
Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping
Låte, Even; Ytterdal, Trond; Aunet, Snorre (Peer reviewed; Journal article, 2020)This brief presents an approach that dynamically exploits content dependencies in asymmetric memory cells. By using a capacitive, logic-value majority circuit and an extra column of memory cells, words are conditionally ... -
Carbon Nanotube Detectors and Spectrometers for the Terahertz Range
Park, Junsung; Liu, Xueqing; Ytterdal, Trond; Shur, Michael S. (Peer reviewed; Journal article, 2020)We present the compact unified charge control model (UCCM) for carbon nanotube field-effect transistors (CNTFETs) to enable the accurate simulation of the DC characteristics and plasmonic terahertz (THz) response in the ... -
Checking of Nanoscale Transistor Models
Hernes, Marie Helene (Master thesis, 2016)A device compact model is a mathematical description of a device, e.g. a transistor, in an integrated circuit. Compact models are designed to be a part of a larger simulation, and work together with a circuit model. For ... -
Comparator-Based Switched-Capacitor Integrator for use in Delta-Sigma Modulator
Torgersen, Svend Bjarne (Master thesis, 2009)A comparator-based switched capacitor integrator for use in a Delta Sigma ADC has been designed. Basic theory about comparator-based circuits has been presented and design equations have been developed. The integrator had ... -
Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology
Hossein Zadeh, Somayeh; Ytterdal, Trond; Aunet, Snorre (Chapter, 2018)Five ultra low voltage and low power full adders have been designed and analyzed with CMOS logic structure. To compare these adders, different metrics including worst case delay, average power, PDP, and PDP*Leakage have ... -
Compensation of Threshold Voltage for Process and Temperature Variations in 28nm UTBB FDSOI
Strandvik, Erlend (Master thesis, 2015)As technology scales down in order to meet demands of more computing power per area, a variety of challenges emerge. Devices with channel lengths of a few nano meters require atomic precision when they are manufactured. ... -
Compiled analog and digital building blocks in 22nm FDSOI
Romero, Marjeris (Master thesis, 2018)This project shows the process of designing a cell library in a 22nm FDSOI process. Part of this project was also to inspect the viability of using a custom layout compiler presented in earlier publications for the 22nm ... -
Current-Mode SAR-ADC In 180nm CMOS Technology
Eilertsen, Bård Egil (Master thesis, 2012)This thesis presents a fully differential 9-bit current-mode successive approximation (SAR) ADC. The circuit is designed in 0.18 um technology with 1.8 V supply voltage and has a current draw on 472 uA. The ADC has a ...