An energy efficient noise-shaping SAR ADC in 28 nm FDSOI
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In a noise-shaping SAR ADC, oversampling and noise shaping are used to increase theconversion accuracy beyond that the SAR exhibits alone. To implement the noiseshaping, the residue voltage present at the SAR DAC plates after each conversionis exploited, and fed into a loop filter connected to an extra input of the SARcomparator. In this thesis, an energy efficient noise-shaping SAR ADC for medical ultrasoundapplications is designed in 28 nm FDSOI. The design specification is minimum 11.0bit ENOB of accuracy, signal bandwidth of minimum 2 MHz, and sample rate ofminimum 32MHz. According to post-layout Monte Carlo simulations, the designedADC has an accuracy of 11.1 bit ENOB, and thus satisfies the accuracy requirement.The signal bandwidth and sample rate are the same as in the design specification.Specifically, the topics of this thesis are the design of the loop filter and its inter-facing towards the SAR, as well as the overall high level design. The 9-bit SAR usedin the system is an already existing implementation. A cascaded FIR-IIR filter topology is used for the loop filter. In this work, thecircuit implementation of this topology is improved, most importantly throughthe introduction of chopped buffers at the filter input. This eliminates signalattenuation due to charge sharing, and a DAC capacitance that is smaller than thesampling capacitance in the loop filter can therefore be used. Also, auto-zeroed,cascoded inverters rather than a standard OTA are used as gain elements in theswitched-capacitor filter structure, and this leads to better energy efficiency. The designed ADC achieves a figure of merit (FOM) of 7.5fJ/conv-step in post-layoutMonte Carlo simulations, and to the best of the author s knowledge, this is betterthan the current state-of-the-art of noise-shaping ADCs. When all kinds of ADCsare taken into consideration, the achieved FOM seems to be similar to the currentstate-of-the-art in the same specification range.