An Ultra-Low Power SAR-ADC in 65 nm CMOS Technology
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This master thesis presents the design, implementation and layout of an ultra-low power 9-bit 1 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS technology. The proposed ADC operates with a supply voltage of 400 mV and the post-layout simulation resulted in a power consumption of 1.22 nW, which is among the best of the currently state-of-the-art ultra-low-power ADCs. Ultra-low power consumption is achieved by utilizing low power transistors with high threshold voltage to minimize leakage power, optimizing the control logic for sub-threshold operation and using a reference digital- to-analog converter with a monotonic switching procedure. The power consumption and resolution of the ADC is mainly limited by the comparator, however, an effective resolution of 8.16 bits is achieved, which results in a figure-of-merit of 4.27 fJ/conversion-step.