Successive Approximation Registers(SAR) Analog to Digital Converters(ADCs) are very power efficient for Effective Number Of Bits(ENOB) below 9 bits. Above 9 bits, low noise comparator current could potentially limit the Figure of Merit(FOM). To achieve good power efficiency for higher ENOB, noise shaping is added to SAR ADC.
A key decision is the choice of loop filter for noise shaping. The main topologies for loop filter are cascaded FIR-IIR, fully passive and error feedback. During the course of the thesis, Noise Shaping SAR ADCs with different loop filters are modelled in Python and designed in schematic level. After comparison of Figure of Merit(FOM), it is found that the error feedback gives best FOM for the given specifications. In addition to giving a sharp noise shaping, error feedback topology has comparator as the only analog component, making it scaling-friendly. The topology also decreases the loop filter capacitance area due to residue amplification before sampling at FIR filter, resulting in low core area. The input referred noise of comparator of approximately 500 $\mu$V is found to be sufficient to get 11b ENOB from model simulations, with 9 bit DAC. SAR ADC based on error feedback loop filter is designed and laid out. The FOM for the ADC on extracted netlist is 13 fJ/conv-step for an ENOB of 10.8 bits, and input frequency of 9.375 MHz. Operating at 160 MS/s, the SAR ADC consumes 509 $\mu$A from 0.85 V supply in 22-nm FDSOI process. The core area of the SAR ADC is 0.0045 mm$^2$.