| dc.description.abstract | The master thesis is carried out in collaboration with Silicon Labs. The main
goal of the thesis is to increase the speed of the CV32E40X processor developed
by openHW group, without increasing the area usage and power consumption by
more than 20%.
The metric used for speed evaluation is Instruction Per Clock Cycle (IPC); for the
area usage - net area, cell area, and total area; for the power consumption - Watts
(W).
The CV32E40X is an open-source RISC-V pipelined processor with four pipeline
stages. The core can execute compressed (16-bit long) and uncompressed (32-
bit long) instructions. The baseline IPC value is 0.46; the baseline net area -
5874.265, the baseline cell area - 16704.66, the total area - 22578.927, the baseline
total power - 270 MicroW.
The thesis addresses how implementing a 2-bit branch prediction unit can improve
the core speed and cost of the improvement in terms of power consumption and
area usage. The results revealed that the 2-bit branch predictor with a cache that
has 8 cachelines increases IPC by 8.7%, at the cost of 8.9% net area, 14.7% cell
area, 13.1% of the total area, and 10.4% total power increase. | |
