| dc.description.abstract | Adder circuits are vital for microprocessors; indeed, apart from the
addition itself, either subtraction, multiplication or division algorithms
may require, at a certain point, the addition of two (partial or not)
operands. For this reason, several architectures have been studied and
improved over the last decades, in order to speed up the aforementioned
operation.
On the other hand, it is well known that having faster circuits means
higher complexity, and, therefore, higher power consumption. In addition
to this, the downscaling process of transistors has increased the
leakage current of these devices, accounting for up to 33% of the total
dissipation, and due to the little capabilities of batteries with
respect to the achievable performance of circuits, the main challenge
of engineers and designers is represented by exploiting low power techniques
so as to decrease the power consumption of electronic devices as
much as possible.
This Master’s Thesis work wants to demonstrate that, when working in
sub-threshold region, it might be possible to employ simple and repetitive
circuits, like ripple carry adders, instead of complex ones, such as
Kogge-Stone architectures, having the same propagation time but with a
significantly lower energy consumption. In this way, it would be possible
to have, at the same time, the performance given by a fast adder and
the area and energy dissipation of the simpler and weaker "anchestor".
As an anticipation, and as it will be seen in the final results, the technology
employed and the choice of the best available architecture resulted
in a great improvement with respect to the study previously conducted.
First of all, with the development of a new full adder circuit (the so called
"XMAJ3"), it is possible to reduce the energy consumption with respect
to ripple carry adders based on both already existing architectures and
on the full adder cell contained in the library. This even without the
employment of customized gates, but only with standard logic blocks
already contained in the library.
Secondly, FDSOI technology makes possible to equalize performance of
serial and parallel adders and, at the same time, saving energy, even
in super-threshold region, allowing to avoid all the problems that subthreshold
design brings. Particularly, for 32-bit based devices, the average
energy saving with respect to the Kogge-Stone adder accounts for
41.48% (with a peak of 56.16%), while for 64-bit adders the mean saving
is 50.02%, with a maximum of 56.83%. | |
