Adder circuits are vital for microprocessors; indeed, apart from theaddition itself, either subtraction, multiplication or division algorithmsmay require, at a certain point, the addition of two (partial or not)operands. For this reason, several architectures have been studied andimproved over the last decades, in order to speed up the aforementionedoperation.On the other hand, it is well known that having faster circuits meanshigher complexity, and, therefore, higher power consumption. In additionto this, the downscaling process of transistors has increased theleakage current of these devices, accounting for up to 33% of the totaldissipation, and due to the little capabilities of batteries withrespect to the achievable performance of circuits, the main challengeof engineers and designers is represented by exploiting low power techniquesso as to decrease the power consumption of electronic devices asmuch as possible.This Master’s Thesis work wants to demonstrate that, when working insub-threshold region, it might be possible to employ simple and repetitivecircuits, like ripple carry adders, instead of complex ones, such asKogge-Stone architectures, having the same propagation time but with asignificantly lower energy consumption. In this way, it would be possibleto have, at the same time, the performance given by a fast adder andthe area and energy dissipation of the simpler and weaker "anchestor".As an anticipation, and as it will be seen in the final results, the technologyemployed and the choice of the best available architecture resultedin a great improvement with respect to the study previously conducted.First of all, with the development of a new full adder circuit (the so called"XMAJ3"), it is possible to reduce the energy consumption with respectto ripple carry adders based on both already existing architectures andon the full adder cell contained in the library. This even without theemployment of customized gates, but only with standard logic blocksalready contained in the library.Secondly, FDSOI technology makes possible to equalize performance ofserial and parallel adders and, at the same time, saving energy, evenin super-threshold region, allowing to avoid all the problems that subthresholddesign brings. Particularly, for 32-bit based devices, the averageenergy saving with respect to the Kogge-Stone adder accounts for41.48% (with a peak of 56.16%), while for 64-bit adders the mean savingis 50.02%, with a maximum of 56.83%.