dc.contributor.advisor | Gjermundnes, Øystein | |
dc.contributor.author | Tobro, Kjersti Hefre | |
dc.date.accessioned | 2019-09-11T11:08:36Z | |
dc.date.created | 2018-11-16 | |
dc.date.issued | 2018 | |
dc.identifier | ntnudaim:18102 | |
dc.identifier.uri | http://hdl.handle.net/11250/2615961 | |
dc.description.abstract | A unit for calculating square root and inverse square root of 32-bit floating-point numbers was designed using SystemVerilog. The unit was made to be incorporated into an existing design for a hardware ray tracer in order to replace software approximations for these functions. The resulting unit calculates the intended functions within the accuracy of the two least significant bits, meaning a maximum relative error of 2.38e-7. The maximum possible frequency of the square root unit was measured at 106MHz on the target FPGA, with a latency of 6 cycles per operation, and a throughput of one operation per cycle. When compared to four other square root architectures, the proposed design was shown to have a lower latency than the compared designs. | en |
dc.language | eng | |
dc.publisher | NTNU | |
dc.subject | Elektronikk, Design av digitale systemer | en |
dc.title | Design of a Single-Precision Floating-Point Square Root Unit for use in a Hardware Ray Tracer | en |
dc.type | Master thesis | en |
dc.source.pagenumber | 66 | |
dc.contributor.department | Norges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi og elektroteknikk,Institutt for elektroniske systemer | nb_NO |
dc.date.embargoenddate | 10000-01-01 | |