Development of a Universal Verification Component for CPU UVM Verification
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The time used debugging and developing testbenches in FPGA and ASIC/IC projects is around 60% of the total time spent in verification. The last years has shown an increase in the adoption of the Universal Verification Methodology(UVM), which can help increase the maximum reuse, and decrease the time spent creating and debugging testbenches. This thesis presents the development of a Universal Verification Component(UVC) for CPU UVM verification. An existing framework has been used as a base in the development. In the project an improvement of the existing sequence items has been done by creating a new sequence item that is functional for several protocols, and can be extended for additional functionality. Specialised functionality, that can be called through tasks, has been moved from the driver and monitor to the interface, which helps create generic components. A task implemented in the interface, which converts signals from the DUT to a sequence item, is called from the monitor and used to write to the analysis ports. There has also been developed a sequencer that is functional for various protocols in the framework. Parameterisation has been utilised for all the components in the hierarchy, in order to grant the specialised functionality for the protocols. The agent, which is parameterised with a configuration object and sequence item, builds the testbench with configuration that has been retrieved from the configuration database, by using the the handle for the various protocols agent to find the correct path.The amount of code lines has been used to quantify some of the efficiency of the UVC, as a decrease in code lines would most likely result in less bugs, and therefore less time spent debugging. There was a total of 28% decrease in amount of code lines for the protocols, when compared to the base framework. 21 files in the framework have also been replaced by the generic components developed in this project. The UVC that has been developed, can be reused in several frameworks with its parameterisation. The framework that adopts the UVC has to set the configuration in the configuration database as presented in this thesis for correct functionality. This UVC can decrease the time used debugging and creating testbenches, and the time saved can help the verification engineer to reach deadline, or be used to further improve the quality of the tests.