Towards Predictable Placement of Standard Cells for Regularly Structured Designs
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Electronic Design Automation (EDA) tools have revolutionised the way digital integrated circuits are being designed. Modern EDA tools are capable of implementing circuits with billions of transistors. An important step in the design flow of digital ICs is the placement of standard cells, where millions of cells are automatically placed on the layout by place and route tools, while adhering to timing, power and congestion constraints. However, a completely automatic flow can have certain drawbacks, especially when it comes to the placing of certain regularly structured designs. These designs are extremely sensitive to delays, and hence, call for a systematic and predictable way of being placed in the layout. This work creates a software framework which enables a designer to effortlessly describe digital circuits and its placement information in a high level language. The program generates a Verilog netlist, a relative placement script and image files corresponding to the design described by the designer. It supports hierarchical designs. It also allows the designer to select the desired library data to be used to implement the netlist. The netlist and the placement script can be read in directly by a place and route tool to create a design exactly as specified by the designer. This can improve the performance of such regularly structured designs. The program was run on three test designs, and all the outputs were generated as expected. Comparisons of the layouts were made in Synopsys® IC Compiler with and without using the generated placement data. Structured designs, as expected, were obtained, when the generated placement script was used.