SAR ADC in 22 nm FDSOI

Abstract

Successive Approximation (SAR) Analog-to-Digital Converters (ADCs) are among the most energy efficient ADCs and has therefore received enormous attention in medical and wireless applications. The great energy efficiency of SAR ADCs are mainly attributed to the downscaling of Complementary Metal-Oxide-Semiconductor (CMOS) circuits, since the SAR architecture benefits greatly by going to smaller and smaller CMOS process nodes. Due to this excellent scaling, the introduction of smaller CMOS nodes opens up for new opportunities and challenges when designing SAR ADCs.

In this thesis, the speed limits of SAR ADCs have been pushed, while high resolution and energy efficiency are maintained. The SAR designed in this thesis is a Nyquist ADC intended for medical ultrasound applications and is designed in a 22 nm Fully Depleted Silicon-On-Insulator (FDSOI) process. The designed SAR ADC is simulated post-layout and the mean Monte Carlo results yields an Effective Number of Bits (ENOB) of 10.2 bits at a sample rate of 100 MS/s. The power consumption is 268 μW and the resulting mean Monte CarloWalden Figure of Merit (FoM) for the ADC is 2.29 fJ/conv.-step. This is currently better than all state-of-the-art ADCs with similar specifications. The ADC designed is also unique in the sense that no one else has managed similar speed and resolution with the same simple pure SAR ADC architecture.

These results are accomplished by using a popular dynamic latch comparator with capacitive loading, improving on already existing bootstrapped switch topology, improvement on already existing Capacitive Digital-to-Analog Converter (CDAC) architecture to greatly increase linearity and still achieve small unit capacitance, a custom made digital circuitry that has very low propagation delay and clock generation based on CDAC bottom plate.