Designing a Virtual Memory System for the SHMAC Research Infrastructure

Abstract

The Single-ISA Heterogeneous MAny-core Computer (SHMAC) is an infrastructure for realizing heterogeneous computing systems. The current SHMAC prototype does not have a Memory Management Unit (MMU). An MMU would simplify the process of providing a process abstraction on the SHMAC and make it possible to run multiple programs at the same time.

This master thesis provides a qualitative comparison of different techniques and solutions for implementing virtual memory. These are discussed with regard to the SHMAC architecture and recommendations are made as to how virtual memory should be implemented in the SHMAC. Specifically, three different designs are identified by locating the address translation hardware either before the L1 cache, after the L1 cache, or before a possibly distributed L2 cache. All three designs seem to be viable alternatives but further investigation is necessary to determine which design is the best fit for SHMAC.