|dc.description.abstract||Electronic paper display (EPD) has reached a position of great maturity. Due to its capability of bistability and great reflectivity, it can display an image without any flowing current. Today, sensors and regulators are being placed out to monitor the real world, and are often battery powered without a display. With the introduction of electronic paper displays, these units can be given a display without a significant increase in power. There is however still very limited power available, and power reduction is considered increasingly important.
A theoretical and practical analysis of EPD, Thin-Film Transistor, and level shifters have been used to investigate power reduction techniques. The area of interest is the sub-circuits where level shifters are adopted. These sub-circuits typically carry over 60% of the total power consumption during an electronic paper write cycle. Practical experiments and simulations have been used to find new power saving level shifters for these sub-circuits.
The simulations have been successfully used to show different level shifters performing and running at two different frequencies (10MHz and 2Hz) using commercially available 180nm technology. The results from the simulations in Cadence Virtuoso have shown that the proposed circuits perform about 80% - 85% better in terms of power at high frequency (10MHz). The results also show that the proposed circuits perform about 65% - 150% worse in terms of power at low frequency (2Hz).
From the results, we have concluded that the proposed circuits are not better in low-frequency applications such as electronic paper displays.
However storage capacitors can be added to electronic paper pixels which can potentially speed up the scan process, thereby making these results more applicable.||