Low-Power Analog-to-Digital Converter Design for In-Probe Ultrasound Imaging Systems

Abstract

The advanced CMOS technology promotes the developments of more portable and efficient ultrasound systems with improved image performance and increased functionality over past several years. An analog-to-digital converter (ADC) plays an important role in advanced ultrasound imaging system to convert continuous analog signals to discrete digital signals. The design of power-efficient, small-area ADCs is necessary for the development of digitization of the in-probe ultrasound three-dimensional (3D) imaging system. This thesis will focus on the design and implementation of powerefficient, small area ADCs working at medium resolution (e.g., 7-10 bit), medium speed (e.g., 30-50MHz). It starts with the design of a low-offset, low-power, high-speed comparator using bulk biasing calibration. The first prototype of ADC is a single-ended binary-weighted 7-bit SAR ADC combined with a double reference technique to reduce area and power. The speed is optimized by an asymmetric delay line embedded in the asynchronous digital logic, enabling a sampling frequency of 40 MS/s. Fabricated in a 65 nm CMOS technology, the ADC is measured to achieve an SNDR of 39.73 dB and an ENOB of 6.3 bit at 1 V supply. It consumes 298.6μW, resulting in a figure of merit (FoM) of 94.74 fJ/conversion-step. The core circuit layout occupies 0.017 mm2. The second prototype, a 8.4-bit ENOB 30MS/s SAR ADC, greatly increases the power and area efficiency by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65nm CMOS technology, the ADC achieves a signal-to-noise ratio (SNDR) of 52.2dB, and consumes 61.3μW at 30MS/s from a 1V supply voltage, resulting in a FoM of 6.2fJ/conversion-step. The core circuit occupies 0.016mm2, the FoM defined by including the area is 0.1mm2•fJ/conversion-step. Intelligent ultrasound systems require a more flexible ADC to benefit for system-level performance. The third prototype extends the ADC design by adding a configurable gain feature, which enables the ADC to maintain a maximum SNDR over a wider input range. A 9-bit configurable-gain SAR ADC was fabricated in a 65nm CMOS technology. Measurement shows that it consumes 46.1μW at 35MS/s from 1Vsupply voltage, and achieves an SNDR of 51dB and an ENOB of8.18bits at Nyquist rate, resulting in a figure of merit (FoM) of4.5fJ/conversion-step. The core circuit occupies 0.009mm2, which is very compact. Moreover, it enables the integration into a low-power ultrasound receiver.