Verification of a Large Heterogeneous Many-core Computer
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The historical trend of steady increase in processor performance with each technology generation has slowed down during the last years due to power limitations. As transistor sizes reduce, the power density on a chip does not remain constant anymore, which is known asthe end of Dennard scaling. This increase of power demand limits the number of transistorsthat can be used simultaneously without exceeding the power budget. This phenomenon,known as the Dark Silicon effect, can be mitigated by building heterogeneous systemscontaining processing elements of different performance and power characteristics. TheSHMAC project at the NTNU aims to provide a platform for investigating heterogeneoussystems at all abstraction levels. Current verification strategies for verifying the hardware parts of the SHMAC platforminclude block-level and top-level testbenches, and bare-metal testing on FPGA. Both ofthem run directed tests that exercise specific features of the design, which are manuallyhandcrafted by each SHMAC developer. This approach not only represents a tedious taskfor the designer, but also does not ensure to reach all corner cases within the design. Inaddition, these verification strategies lack of coverage metrics that measure verificationprogress and quality, and do not provide mechanisms to effectively identify and track bugsin the design. This project proposes a new verification framework and methodology for the SHMACplatform using the Universal Verification Methodology (UVM). This new methodologyis aimed to overcome the limitations of the existing verification strategies previously presented, and also is intended to provide highly reusable verification environments. Thelatter plays an important role in reducing the effort and time spent on creating new tests asthe design complexity of the SHMAC platform increases and new extensions are implemented.