Verification of a Large Heterogeneous Many-core Computer

Abstract

The historical trend of steady increase in processor performance with each technology generation has slowed down during the last years due to power limitations. As transistor sizes reduce, the power density on a chip does not remain constant anymore, which is known as the end of Dennard scaling. This increase of power demand limits the number of transistors that can be used simultaneously without exceeding the power budget. This phenomenon, known as the Dark Silicon effect, can be mitigated by building heterogeneous systems containing processing elements of different performance and power characteristics. The SHMAC project at the NTNU aims to provide a platform for investigating heterogeneous systems at all abstraction levels.

Current verification strategies for verifying the hardware parts of the SHMAC platform include block-level and top-level testbenches, and bare-metal testing on FPGA. Both of them run directed tests that exercise specific features of the design, which are manually handcrafted by each SHMAC developer. This approach not only represents a tedious task for the designer, but also does not ensure to reach all corner cases within the design. In addition, these verification strategies lack of coverage metrics that measure verification progress and quality, and do not provide mechanisms to effectively identify and track bugs in the design.

This project proposes a new verification framework and methodology for the SHMAC platform using the Universal Verification Methodology (UVM). This new methodology is aimed to overcome the limitations of the existing verification strategies previously presented, and also is intended to provide highly reusable verification environments. The latter plays an important role in reducing the effort and time spent on creating new tests as the design complexity of the SHMAC platform increases and new extensions are implemented.