Extended Bubble Razor Methodology and its Application to Dynamic Voltage Frequency Scaling Systems
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Increasing voltage and frequency margins in traditional worst-case designs will be more dominating as the process technology is scaled, where power is wasted in exchange for production yield. We have investigated a state-of-the-art DVFS method to eliminate all margins and still guarantee error-free operation, named Bubble Razor. In the first part of the project did we investigate the methodology of automated conversion from a flip-flop design to a two-phased latch circuit and finally a complete Bubble Razor circuit. The second part was investigating how Bubble Razor behaves in circuits with synchronous clock domain-crossings, and revealing a clock domain-crossing problem. Two new types of clock-gates are proposed, extending Bubble Razor and enabling it to operate in designs with clock-gates and multiple synchronous clock domains. A conventional flip-flop design was converted to a two-phase latch design and got a Bubble Razor inserted. Bubble Razor enabled the design to operate at 80% of the flip-flop version's voltage, without any errors.