| dc.description.abstract | As technology scales down in order to meet demands of more computing power per area, a variety of challenges emerge. Devices with channel lengths of a few nano meters require atomic precision when they are manufactured. Small irregularities in the equipment and manufacturing environment can cause large process variations from die--to--die, but also within--die variations. Along with the increasing density of transistors per die which has led to severe performance issues due to temperature variations, these effects may seriously impact operation and cause large deviations in frequency and power across a the chip.
This thesis will present the analysis and design of a circuit with the goal of compensating the threshold voltage, by means of body biasing, in order to mitigate process and temperature variations. The compensation circuit is designed to provide adaptive body biasing for a large number of equally matched devices within the chip, which may be useful in digital systems with many repetitive instances. Its functionality and effect will be tested by designing it to be used with a 13--stage inverter based ring oscillator operating at 65.5MHz, and observing the improvement in frequency variation across processing corners and a temperature range from -40 degrees Celsius to 80 degrees Celsius. All circuits were designed using a commercially available 28nm fdsoi transistor technology because of its excellent susceptibility to body biasing, and its promise as a competitive technology to continue Moore`s law.
Results obtained by post--layout simulations on the ring oscillator show that frequency variations across processing corners and temperature has been reduced from 18.69% down to 0.632% by utilising adaptive body biasing provided by the compensation circuit. Ring oscillator frequency temperature sensitivity in a range from -40 degrees Celsius to 80 degrees Celsius for the typical corner is shown to be as little as 29.4ppm per degree Celsius | |
