Implementation of Biomedical Algorithm on the SHMAC Platform

Abstract

Biomedical applications are becoming more and more important as they can improve the life conditions of millions of people around the world. Implementing them on low power embedded systems is a very challenging task as many among them demand numerous signal intense calculations. A major part of the epilepsy prediction algorithm proposed by Iasemidis et al. [2] called Short Term Maximum Lyapunov Exponent belongs to this category and comprises the study subject of this thesis. The algorithm is ported to be executed on the single-ISA Many-core Computer (SHMAC) developed at NTNU, which is an evaluation platform for studying heterogeneous, power constrained systems. Different software versions of the algorithm (floating-point, fixed-point and hybrid), written in C language, are compared to each other and the most suitable ones are profiled and considered for further investigations. Corresponding hardware modules that implement the main bottleneck in each version are designed in VHDL hardware description language, and compared against each other. The most efficient module turns out to be an accelerator for the hybrid software version. This is selected to be further integrated within the SHMAC infrastructure, in order to evaluate its impact on the overall behavior of the algorithm and the target platform. The performance, area usage, power and energy consumption as well as the energy efficiency are evaluated with or without the use of the hardware accelerator. Although that at the end of the thesis the application s real-time requirements were not met, the mixed (hardware/software) implementation that makes use of the accelerator, turns out to be 66% faster and 88% more energy efficient compared to the corresponding pure software implementation. Considerations about further modifications that can allow real-time performance are also discussed.