Ultra low voltage combinatorial logic building blocks
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In this project the three logical gates inverter, 2-input NAND and 2-input NOR was created. Each gate was implemented with two different topologies. All gates created were able to operate with a supply voltage below the transistors threshold voltage. Due to this, the gates created in this project can be called sub-threshold logical gates. To ensure that all voltages were sub-threshold a brief investigation of the transistors were performed, to determine some of the transistor characteristics. All gates were created at a schematic level and they were tested with both DC and transient analyses. The analyses were performed on different transistor sizes and with different supply voltages, to uncover how transistor gate sizes and supply voltage affects the logical gates. The different gate topologies were compared to each other, and a body biased gate was compared to unbiased gates. The results from the simulations performed showed that it is possible to make logical gates operate at sub-threshold voltages. The ultra low voltage caused the gates to be prone to noise, process variations, have a large gate area and large delay. Using alternative gate topologies and different gate sizes can mitigate delay and process variations, but will also take up a larger gate area and consume more energy. By using body biasing the gate area and energy consumption could be decreased without affecting gate balance, noise margins and process variations. The main method for testing the devices in this project has been to run large parametric analyses covering a wide variety of transistor sizes and supply voltages. This method have resulted in a thorough, but time consuming investigation. Because of this the scope of this project was limited to theoretical schematic analyses, and layout with parametric extractions were not included.