| dc.description.abstract | Video noise is an important issue even in modern camera sensors. The trend of higher resolutions and more FPS makes real time video processing in general a difficult task. In this study, the goal was to find a fast video denoising algorithm, which can be implemented on an FPGA without using an exaggerated amount of its available resources. A selection of algorithms were therefore reviewed, varying from some of the most basic to some of the most acknowledged. One of them, the Yaroslavsky filter, was selected because of its simple approach to the well recognized method of using only the most similar and close neighbor pixels in the average and noise removal process. Three modifications to the original Yaroslavsky was proposed, and implemented in Matlab for simulations. The first, and maybe most important modification, was to extend the algorithm from the spatio, to the spatio-temporal domain. This modification makes the algorithm something more than a image denoising algorithm applied on each independent frame in a video. The temporal extension utilizes the correlation between pixels in successive frames. The second modification was to introduce fuzzy thresholds, instead of the binary thresholds in the original Yaroslavsky. This makes the algorithm more adjustable, so it can mimic the more advanced Bilateral filter. The third modification proposed, was to make the Yaroslavsky capable of removing impulse noise. The original Yaroslavsky filter would in case of impulse noise, not detect any similar neighbor pixels, and thus leave it alone. The proposed modification was to introduce median filtering in such cases. The modified Yaroslavsky algorithm have been tested in Matlab, and compared with the original Yaroslavsky, as well as with the algorithm proposed in the preliminary project work. The simulation results showed that the proposed modified Yaroslavsky achieved the best results. VHDL was therefore used making an FPGA implementation of the algorithm. The proposed implementation consists of five components, and has four pipeline stages. The implementation was simulated in Modelsim to ensure correct manner of operation. It was then synthesized for an Altera Cyclone III FPGA, using both Quartus and Synplify. The highest clock frequency achieved was 87.7MHz, using 1044 logic elements, 345 registers, and 5 DSP blocks. | nb_NO |
