Lossless video compression in an FPGA for reducing DDR memory bandwidth usage

Abstract

We show that a hardware implementation of a lossless image compression schemecan be used as means for lowering DDR memory bandwidth usage from a videostream. A prediction scheme based on LOCO-I is used to reduce correlative redundancybetween sequential pixels, before the data is encoded by Golomb coding.The data packages after source coding contain a continuous stream of prefix codes,in order to eliminate the header data imposed by more advanced packing schemes.This in turn results in a higher demand on the decoding side in terms of resourceusage, because of the need for high parallelism when a new prefix code is countedand decoded each clock cycle.The test images are reduced in size by 49-84%, depending on their inherent complexity.Resource consumption for this design amounts to 10100 Logic Elements(synthesized for an Altera Cyclon III FPGA - EP3C80F484C6), with a operatingfrequency of 152,86 MHz for a throughput of 458 MB/s. These numbers can beimproved by reducing the algorithm complexities. LE usage is reduced to 4695,while accomplishing a image size reduction of 34-59%.We present a way to increase decompression throughput by adding parallel decodermodules. Those changes will increase throughput to a multiple of 458 MB/s whileworsening the compression somewhat. LE cost increases depending on the level ofparallelism.