Low Energy Implementation of Robust Digital Arithmetic in Sub/Near-Threshold Nanoscale CMOS: For Ultrasound Beamforming
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This thesis will show combinatorial digital design using the 65nm transistor technology operating in near/sub-threshold region. Designing a 16By9Bit adder optimized with regard to power consumption with a speed requirement of 50MHz per operation for micro-beamforming. To optimize the addition of the 16, 9 bit numbers, studies of different building block are performed to find the best building blocks optimized for low power consumption, robustness and regular layout design without breaking the speed requirement. A new digital building block for standard digital building blocks optimized for subthreshold performance are proposed. In addition there will be shown a way to make regular layout designs.As a final result there will be shown a 16by9bit adder layout design with a delay equal to 17.7nS = 56.5MHz with a power consumption of 25uW at 20degrees and delay equal to 10nS = 100MHz with a power consumption of 36.2$uW at 80degrees. The design are build up from 6736 transistor and uses a area of 240um * 84um = 20.1mm^2.