Evaluation of state-of-the-art Huffman decoding algorithms and their asynchronous implementation using BALSA
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This report presents the design of an asynchronous Huffman decoder, implemented in the Balsa synthesis system. Power consumption, speed and area figures from the post layout design have been measured. In addition, a synchronous design was implemented in order to compare to the asynchronous design. When running at the same clock frequency, it was found that the asynchronous is faster and more power efficient than the synchronous design. However, at the maximum clock frequency for each design, the synchronous design has a higher throughput than the asynchronous design. It was also found that the asynchronous design has an area cost 10 times greater than the synchronous design. In theory, asynchronous circuits is faster and more power efficient than synchronous circuits, however this comes at an area and complexity overhead. In the case of the Huffman decoder implemented in this thesis, the benefits are not enough to compensate for the very large area increase.