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dc.contributor.advisorYtterdal, Trondnb_NO
dc.contributor.authorLøvseth Finnøy, Torbjørnnb_NO
dc.date.accessioned2014-12-19T13:46:57Z
dc.date.accessioned2015-12-22T11:45:47Z
dc.date.available2014-12-19T13:46:57Z
dc.date.available2015-12-22T11:45:47Z
dc.date.created2011-11-14nb_NO
dc.date.issued2011nb_NO
dc.identifier456222nb_NO
dc.identifierntnudaim:6392
dc.identifier.urihttp://hdl.handle.net/11250/2370331
dc.description.abstractThis master thesis presents the investigation and design of a capacitor reset circuit. The circuit was implemented and simulated using a standard 0.35µm CMOS process. A capacitive load of 20pF should be reset at 0.1% accuracy within 500ns, preferably around 250ns. The supply voltage varies from 2.5V to 3.6V , and the input reference voltage ranges from 0.15Vddto 0.85Vdd. Main goal was to fulfill these requirements with minimum area. Three promising amplifier topologies was identified and evaluated in detail. Two of these consisted of two complementary two-stage opamps in parallel, and were selected for implementation and simulation. Best results were produced by an amplifier using current positive-feedback slew rate enhancement technique.Eldo simulations resulted in reset times down to 58.08ns and settling accuracies as low as 0.0012%. Process corner simulations gave a worst case accuracy of 1.15% and a settling time up to 553.33ns. Both accuracy and settling time worst cases are larger than required by the given specification. Estimated active area was calculated to 31.77µm.nb_NO
dc.languageengnb_NO
dc.publisherInstitutt for elektronikk og telekommunikasjonnb_NO
dc.subjectntnudaim:6392no_NO
dc.subjectMTEL elektronikk
dc.subjectAnalog og blandet design
dc.subject
dc.titleA High Speed Low Cost Capacitor Reset Circuitnb_NO
dc.typeMaster thesisnb_NO
dc.source.pagenumber96nb_NO
dc.contributor.departmentNorges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for elektronikk og telekommunikasjonnb_NO


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