A High Speed Low Cost Capacitor Reset Circuit
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This master thesis presents the investigation and design of a capacitor reset circuit. The circuit was implemented and simulated using a standard 0.35µm CMOS process. A capacitive load of 20pF should be reset at 0.1% accuracy within 500ns, preferably around 250ns. The supply voltage varies from 2.5V to 3.6V , and the input reference voltage ranges from 0.15Vddto 0.85Vdd. Main goal was to fulfill these requirements with minimum area. Three promising amplifier topologies was identified and evaluated in detail. Two of these consisted of two complementary two-stage opamps in parallel, and were selected for implementation and simulation. Best results were produced by an amplifier using current positive-feedback slew rate enhancement technique.Eldo simulations resulted in reset times down to 58.08ns and settling accuracies as low as 0.0012%. Process corner simulations gave a worst case accuracy of 1.15% and a settling time up to 553.33ns. Both accuracy and settling time worst cases are larger than required by the given specification. Estimated active area was calculated to 31.77µm.