dc.contributor.advisor | Hanche-Olsen, Harald | |
dc.contributor.author | Svedenborg, Stian Valentin | |
dc.date.accessioned | 2015-10-06T10:56:49Z | |
dc.date.available | 2015-10-06T10:56:49Z | |
dc.date.created | 2014-09-19 | |
dc.date.issued | 2014 | |
dc.identifier | ntnudaim:10692 | |
dc.identifier.uri | http://hdl.handle.net/11250/2352587 | |
dc.description.abstract | This thesis explores the challenges of implementing an instruction cache side-channel attack on an ARM platform. The information leakage through the instruction cache is formally discussed using information theoretic metrics. A successful Prime+Probe instruction cache side-channel attack against RSA is presented, recovering 967/1024 secret key bits by observing a single decryption using a synchronous spy process. Furthermore, an unsuccessful attempt is made at decoupling the spy from the victim. Finally, the current state of countermeasures against soft ware based cache side-channel attacks are summarised. | |
dc.language | eng | |
dc.publisher | NTNU | |
dc.subject | Fysikk og matematikk, Industriell matematikk | |
dc.title | Exploring Instruction Cache Analysis - On Arm | |
dc.type | Master thesis | |
dc.source.pagenumber | 79 | |