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dc.contributor.advisorHanche-Olsen, Harald
dc.contributor.authorSvedenborg, Stian Valentin
dc.date.accessioned2015-10-06T10:56:49Z
dc.date.available2015-10-06T10:56:49Z
dc.date.created2014-09-19
dc.date.issued2014
dc.identifierntnudaim:10692
dc.identifier.urihttp://hdl.handle.net/11250/2352587
dc.description.abstractThis thesis explores the challenges of implementing an instruction cache side-channel attack on an ARM platform. The information leakage through the instruction cache is formally discussed using information theoretic metrics. A successful Prime+Probe instruction cache side-channel attack against RSA is presented, recovering 967/1024 secret key bits by observing a single decryption using a synchronous spy process. Furthermore, an unsuccessful attempt is made at decoupling the spy from the victim. Finally, the current state of countermeasures against soft ware based cache side-channel attacks are summarised.
dc.languageeng
dc.publisherNTNU
dc.subjectFysikk og matematikk, Industriell matematikk
dc.titleExploring Instruction Cache Analysis - On Arm
dc.typeMaster thesis
dc.source.pagenumber79


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