• Automated Desynchronization Using Pyverilog 

      Rotevatn, Synnøve Andersen (Master thesis, 2021)
    • Conversion of a simple Processor to asynchronous Logic 

      Vee, Bjørn Thomas Søreng (Master thesis, 2014)
      This paper discuss the conversion of a simple 16-bit synchronous RISC based processor into asynchronous logic. The most important targets were the simplicity of the conversion, to see how the tools reacted to asynchronous ...
    • Register file optimisation 

      Sørvik, Henrik Sundkøien (Master thesis, 2017)
      The increasing demand for low-power solutions and small area usage makes it necessary to explore power efficient solutions for critical parts of a system as the data storage in the register file. The register file is an ...
    • Towards Predictable Placement of Standard Cells for Regularly Structured Designs 

      Paldas, Auritro (Master thesis, 2018)
      Electronic Design Automation (EDA) tools have revolutionised the way digital integrated circuits are being designed. Modern EDA tools are capable of implementing circuits with billions of transistors. An important step in ...