Register file optimisation

Abstract

The increasing demand for low-power solutions and small area usage makes it necessary to explore power efficient solutions for critical parts of a system as the data storage in the register file. The register file is an array of registers capable of storing data. This thesis explores two different approaches to optimise the register file. The first approach exploits the regular structure of a register file. By making a generator that makes relative placement directives, it is possible to place the cells of the register file in a regular structure. This is done using a placement tool that uses these directives to place the register file cells, instead of letting the tool do the placement optimisation. The second approach looks at the architecture of the memory cells of the register file. The selection logic is one-hot encoded and two latch based designs are implemented to reduce both power consumption and area usage. Both latch based designs utilises the fact that a flip-flop can be modelled as a pair of a master latch and a slave latch. By sharing either the slave latches or the master latches, the number of latches needed for the register file is reduced. A Shared Master-latch design and a Shared Slave-latch design are implemented. All the designs are validated after implementation using existing testbenches designed for the system that the register file is a part of. The designs are synthesized and the power consumption are estimated in order to evaluate the optimisation compared to the original, flip-flop based register file. The one-hot encoding of the selection signal proved to reduce the activity of the register file with 38.67 percent, thus reducing the dynamic power consumption with 38.41 percent. The latch based designs further improved the power consumption in the register file, with the Shared Master-latch design most ef- ficient with an improvement of 53.42 percent on the original design and 24.36 percent on the one-hot encoded design. The Shared Slave-latch design deemed an improvement of 46.75 percent on the original design and 13.55 percent on the one-hot encoded design. In terms of area usage showed the results that the Shared Slave-latch design was most efficient. Mostly because latches are smaller than flip-flops and that the Shared Master-latch design added extra latches to delay some of the logic. In the end did the Shared Slave-latch design uses 13.93 percent less area than the original design, and the Shared Master-latch design uses 9.97 percent less. On the other hand, did the area usage increase by 6.66 percent in the design with the one-hot encoded selection logic.