Register file optimisation
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The increasing demand for low-power solutions and small area usage makes itnecessary to explore power efficient solutions for critical parts of a system as thedata storage in the register file. The register file is an array of registers capableof storing data. This thesis explores two different approaches to optimise theregister file.The first approach exploits the regular structure of a register file. By makinga generator that makes relative placement directives, it is possible to place thecells of the register file in a regular structure. This is done using a placementtool that uses these directives to place the register file cells, instead of letting thetool do the placement optimisation.The second approach looks at the architecture of the memory cells of theregister file. The selection logic is one-hot encoded and two latch based designsare implemented to reduce both power consumption and area usage. Both latchbased designs utilises the fact that a flip-flop can be modelled as a pair of amaster latch and a slave latch. By sharing either the slave latches or the masterlatches, the number of latches needed for the register file is reduced. A SharedMaster-latch design and a Shared Slave-latch design are implemented. All thedesigns are validated after implementation using existing testbenches designedfor the system that the register file is a part of. The designs are synthesizedand the power consumption are estimated in order to evaluate the optimisationcompared to the original, flip-flop based register file.The one-hot encoding of the selection signal proved to reduce the activity ofthe register file with 38.67 percent, thus reducing the dynamic power consumptionwith 38.41 percent. The latch based designs further improved the powerconsumption in the register file, with the Shared Master-latch design most ef-ficient with an improvement of 53.42 percent on the original design and 24.36percent on the one-hot encoded design. The Shared Slave-latch design deemedan improvement of 46.75 percent on the original design and 13.55 percent on theone-hot encoded design.In terms of area usage showed the results that the Shared Slave-latch designwas most efficient. Mostly because latches are smaller than flip-flops and thatthe Shared Master-latch design added extra latches to delay some of the logic. Inthe end did the Shared Slave-latch design uses 13.93 percent less area than theoriginal design, and the Shared Master-latch design uses 9.97 percent less. Onthe other hand, did the area usage increase by 6.66 percent in the design withthe one-hot encoded selection logic.