| dc.description.abstract | The demand for low-power and energy-efficient digital systems has increased in recent years
for various applications. Ultra-low-voltage circuits have become popular in low-power applic-
ations but face performance degradation. This report analyzes the operation of static CMOS
and Schmitt trigger (ST) CMOS-based full adders, full adders connected as ring oscillators,
and ripple carry adders in the subthreshold region. Full adder implementation using Schmitt
trigger CMOS XOR can save 50% average power as compared to full adder implementation
using static CMOS XOR, while full adder implementation using Schmitt trigger CMOS NAND
gate can save 31% average power as compared to full adder implementation using static CMOS
NAND gate at TT corner, 0.18V and 27°C. Additionally, the report provides a complete DC
voltage transfer analysis with analytical expressions for the N MH and N ML. A comparison
between the ST CMOS and static CMOS adders reveals the relative benefits, such as a high
and stable noise margin, with the temperature rise, while presenting drawbacks, such as larger
size requirements of each in ULV applications. Propagation delay is higher for Schmitt trigger
CMOS full adders than static CMOS full adders for all process corners at 0.18V and 27°C.
Furthermore, the study includes a thorough investigation of measured propagation delay, av-
erage power, power delay product, and energy-delay product of the circuit when full adders
are connected in the ring configurations and also in the ripple carry adders configuration.
In-ring oscillators at TT corner, 0.18V and 27°C, ST CMOS NAND save 16% average power
than static CMOS NAND, ST CMOS XOR save 66% average power than static CMOS XOR
configuration. In the RCAs at TT corner, 0.18V and 27°C, ST CMOS NAND saves 43% av-
erage power than static CMOS NAND, ST CMOS XOR saves 53% average power than static
CMOS XOR configuration.
Keywords: Schmitt trigger, Static, Subthreshold, CMOS, N MH , N ML, delay, Power,
PDP, EDP, Ring, RCA. | |
