Abstract
Despite the introduction of IEEE 1800-2017, a language standard for hardware description
and verification that aims to improve on IEEE Standard 1364-2005, tool support for some
useful features of the hardware description and verification language have been notably slow.
Implementation of the interface construct by Electronic Design Automation (EDA) tool
vendors and maintainers vary and hence can be a daunting task for silicon engineers during
Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)
development.
This thesis presents corner cases where EDA tools used in the ASIC/FPGA design flow
provide limited or no support for features of the SystemVerilog language with a focus on their
interaction with SystemVerilog Interfaces in synthesizable designs. Failure messages reported
by the tools are analyzed to determine their accuracy and compliance with the IEEE Standard
1800-2017.
Efforts are made to employ the most recent versions of EDA tools in this work to ensure
that the findings are current and a true reflection of the level of tool support from vendors or
tool maintainers. Proprietary and open-source tools widely used in industry and academia
are used to ensure that a large community benefits from the findings of this thesis.
This report provides a goto document detailing support for interface features in EDA
tools used in the ASIC/FPGA toolchain. This provides a list of features silicon engineers and
people in academia should avoid when using some EDA tools for ASIC/FPGA development
thereby ensuring better collaboration between teams. EDA tool vendors and maintainers
benefit from this work via Nordic Semiconductor from the filing of unexpected tool behaviour.
The general digital design community could again benefit from this work by pressing tool
vendors to implement these features in future tool revisions.