Data transfer and memory usage can have a significant impact on power consumption in computing systems. Inefficient data transfer mechanisms or excessive data transfer operations can
result in higher power consumption. Data transfer and memory are also interconnected, with
efficient data transfer often relying on sufficient memory to temporarily store data during transfer. Optimizing both data transfer and memory performance is essential for maximizing the
overall performance and usability of a computer system. Direct Memory Access(DMA) controllers play a crucial role in chip performance. The DMA controller is used to transfer the data
blocks between memory locations and external devices without interrupting the execution flow
of the CPU. DMA is used to increase the overall system performance by reducing the load on the
CPU. The DMA controller performs bus transactions with low power consumption compared to
bus transactions performed by the microcontroller.
This thesis presents power optimization techniques for DMA controllers and information regarding the power consumption and energy consumption of DMA controllers with different
buffer widths. The simulation waveforms for the DMA controller with different buffer widths
are provided. The existing DMA controller is modified to incorporate the identified power optimization techniques. The power consumption and energy consumption values for the existing
and modified DMA controllers are measured. The power consumption of a DMA controller increases when the buffer width increases due to the amount of data transferred in each cycle. The
power consumption values table is presented with power consumption values of high and low
activities at different time intervals. Compared to the existing DMA controller, results show a
reduction of energy consumption by 37% and 60% for 16-bit and 32-bit DMA controllers. When
the buffer width of a DMA controller is doubled the energy consumption reduces due to less
number of bus transfers for data transmission.
