Implementing Open flow switch using FPGA based platform
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OpenFlow based SDN, is currently implemented in various networking devices and software, providing high-performance and granular traffic control across multiple vendors network devices. OpenFlow, as the first standard interface designed specifically for SDN, has gained popularity with both academic researchers and industry as a framework for both network research and implementation. OpenFlow technology separates the Control Plane from the Data Path and this allows the network managers to develop their own algorithms to control data flows and packets. Several vendors have already added OpenFlow to their features such as HP Labs,Cisco researchers, NEC, etc. Currently, OpenFlow Switch is already implemented on several different platforms e.g, in software (Linux, Open-WRT) and hardware (NetFPGA). More and more researchers implement the switch on FPGA-based platform, because FPGA-based platform is flexible, fast and reprogrammable. However, there are limited number of studies about the performance of the OpenFlow switch, which motivates this project. In order to do the research of OpenFlow performance, the simulation model of OpenFlow system is implemented in this project. The main objective of this project has two sides. On one hand, it is to implement OpenFlow system (switch and controller) using a hardware language on FPGA-based platform. On the other hand, it is also to measure the performance metrics of the OpenFlow switch, especially the service time (switch and controller) and the sojourn time. More specifically, data plane and control plane are both implemented on FPGA-based platform. It is designed in VHDL language by ISE design tools. FPGA-platform is Virtex6 type from Xilinx. It is observed from the results that the service time and the sojourn time both have almost linear increase with the increase in payload size. Moreover, the results indicate that the switch takes 2 clock cycles to respond to the writing request of the controller.