|dc.description.abstract||Energy efficiency in electronic system designs has been playing an important role for years. With the increased usage of battery powered devices and the increased number of functionalities they provide, energy efficiency has become a crucial demand. Modern devices store or transmit data for various purposes. To make the process of data handling more efficient, The Discrete Cosine Transform, DCT, compression algorithms are used extensively. However, the conventional DCT computations require multipliers and memory modules which makes the algorithm energy inefficient.
This thesis presents investigation and testing of the proposed energy efficient DCT algorithm. The proposed algorithm is compared with other popular but less energy efficient solutions. This comparison showed that a trade-off between the quality of results and energy efficiency is inevitable. The algorithm implementation in hardware is presented with an additional power saving technique employed early at the design flow. The implementation requires only 14 adders. No multipliers or memory modules are required. Divisions which are necessary in the inverse DCT are handled in such way so the hardware processes only integer numbers.
The proposed hardware is implemented in ASIC tools in STM 65nm technology. The DCT module occupies 181.425 μm x 176.8 μm in total, consumes dynamic power of 17.88 mW and leakage power of 323 uW. These numbers describe the design synthesized for a clock frequency of 1 GHz, a supply voltage of 1V and a temperature of 25 °C. The energy estimation of 190 pJ is found for the same design conditions assuming the processing of one input 8 by 8 pixels block. Results are included for the inverse DCT module as well.
The design flow with power simulations and power optimization techniques is presented in both synthesis and place and route phase. The design is synthesized for different frequencies ranging from 200 MHz to 1.43 GHz, for different temperatures of 125°C and 25°C, for different voltage supplies ranging from 0.82V to 1.10V. Along with those changes, the dynamic power changes from 15.1 mW to 1.7 mW, the leakage power changes from 10.6 mW to 0.2 mW and the energy changes from 136 pJ to 459 pJ assuming the processing of one input 8 by 8 pixels block. Tables showing this is detail are included.
The designed modules are interfaced with the AHB bus and a protocol for communication and DCT calculations is described. The effectiveness of calculating the DCT in hardware is shown by comparing it with a possible software implementation. This analysis showed that the solution in hardware is 5 times faster for a particular case of 8b wide pixels and 32b wide AHB bus.||en