| dc.description.abstract | The growing focus on systems which largely depend on sensor technology have recently experienced increased interest. Some applications are autonomous cars, bodyworn sensors, Internet of Things, In vivo sensory systems and gesture based systems. These applications require a high number of sensor channels to make complex decisions. Meanwhile, they have tight space constraints because of embedded use. Removing unwanted noise from such sensor systems with large number of channels require high throughput filtering in addition to having low area. Therefore, this thesis has explored, implemented and validated architectures for high throughput sensor filtering systems containing large number of independent Analog to Digital Converters (channels). These architectures were area constrained to utilize low area and be a part of a Microcontroller. A 2nd order Cascaded Integrator-Comb filter was used to illustrate large intermediate storage requirements on large number of channels. Applying Hogenauer bit-pruning on this filter gave a 15.5% load/store bus width reduction compared to an earlier proposed High Throughput Architecture which used full-width Cascaded Integrator-Comb. A double-clocked static-Random Access Memory (SRAM) and a split-SRAM architecture, both being independent of filter combinatorial path were proposed and implemented using Hardware Desciption Language. A new SRAM block selector and internal address translator algorithm was also proposed and mathematically proven for usage in fixed LOAD/STORE split-SRAM architectures. After implementation on Nexys4DDR, the double clocked SRAM architecture resulted in a 5 stage pipeline, achieving 92.6% pipeline utilization, 1168 lookup-tables+slices, 64MHz fmax and 1.08 cycles/channel throughput at 50 channels. The split-SRAM architecture used a 3 stage pipeline, achieved 96.1% pipeline utilization with 1039 lookup-tables+slices, 90MHz fmax in addition to being shown feasible for block-RAM usage. Both architectures solved current system challenges. In addition, the two architectures achieved a 3.57% and 7.71% decrease in processing time compared to previously proposed High Throughput Architecture. Split-SRAM architecture was shown to be the most suitable design for future system integration because of timing benefits. Evaluation of Run Length Encoding, Compressive sampling and Delta encoding in the application of sensor filtering systems with multiple channels was also performed and concluded to be sensor application dependent. It was therefore omitted in this general sensor system context, but possible bit-savings were estimated for delta encoding was presented for further studies. | en |
