Automatic Dynamic Clock Gate Analysis

Abstract

The clock gate is a logic cell seen in most modern electronic integrated circuits. The clock gate is used to stop a clock signal from propagating through the circuit, and hence minimize dynamic power consumption. Clock gates are normally automatically inserted by a synthesis tool based on a set of criteria. The synthesizer translates Register Transfer Level (RTL) code into a list of corresponding physical components and the connections between them. Though the synthesizer strives to insert efficient clock gates that help increase the quality of the system, it is suspected that some clock gates are inefficient and could be improved by a digital designer manually by altering the source RTL design.

During the work on this thesis a software program named CGAnalyzer was developed that automates the process of locating inefficient clock gates. Such a program is necessary because there can be thousands of clock gates within a digital design, and each needs to be looked at individually to be able to judge its degree of efficiency. CGAnalyzer use the product of synthesis to trace a connection between each clock gate and the registers that it drives. A simulation tool is then used to see the behavior of the clock gate and registers together, based on any testbench that the designer would like to run. The behavior is analyzed, and a report for the designer to read is created.

The CGAnalyzer's resulting output turned out according to specification. The readable text file points to inefficient clock gates, giving the user information about all the statistics that it is evaluated on. It also provides the full hierarchical path of the clock gate, and each of the registers that it drives. The software also finds the best clock gates for comparison, as well as reporting the average statistics for the whole design.

A test of the relevance of the output file was conducted to find out whether or not the results from the analysis points at actual inefficient clock gates that need optimization. The very first clock gate that was manually analyzed was found to be flawed and in need of optimization. After a change of the logic controlling the clock gate enable-signal the clock gate was only opened when a change of the registers was needed.