FPGA Video Stream Communication System

2016

Video processing systems consist mostly of large designs highly critical in synchronisation

and delays of data transfers. In this thesis is introduced the design of an FPGA Video Stream

Communication System. It will provide stream data communication between an external source

such as a video camera or external PC, and store them to DDR3 memory, so that further on they

can be accessed by the video encoding module.

For the first part of the communication consisting between the external source and DDR3

memory, protocols such as Ethernet and PCI have been implemented. The data is stored in the

memory via the AXI DMA interface. In the second part of the stream data transfer, the communication

between the DDR3 and video encoding module was facilitated with the implementation

of AXI DMA. The third phase of this project consisted in assembling all the design and testing

whether the stream data transfer was accurate and efficient for various data length and as well

in read and write directions. The design and tests were performed in Xilinx FPGA Kintex 7, and

Vivado 15.4 was the tool used in the stages of the design.

This design will be implemented in a larger Post-Doctoral project exploiting Video Transcoding

System Architectures and Optimisation Techniques susceptible to Dynamic Partial Recon-

figuration.

NTNU