FPGA Video Stream Communication System
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Video processing systems consist mostly of large designs highly critical in synchronisationand delays of data transfers. In this thesis is introduced the design of an FPGA Video StreamCommunication System. It will provide stream data communication between an external sourcesuch as a video camera or external PC, and store them to DDR3 memory, so that further on theycan be accessed by the video encoding module.For the first part of the communication consisting between the external source and DDR3memory, protocols such as Ethernet and PCI have been implemented. The data is stored in thememory via the AXI DMA interface. In the second part of the stream data transfer, the communicationbetween the DDR3 and video encoding module was facilitated with the implementationof AXI DMA. The third phase of this project consisted in assembling all the design and testingwhether the stream data transfer was accurate and efficient for various data length and as wellin read and write directions. The design and tests were performed in Xilinx FPGA Kintex 7, andVivado 15.4 was the tool used in the stages of the design.This design will be implemented in a larger Post-Doctoral project exploiting Video TranscodingSystem Architectures and Optimisation Techniques susceptible to Dynamic Partial Recon-figuration.