| dc.description.abstract | A microcontroller can only offer a limited amount of communication interfaces. When designing an ASIC targeted for high volume production, flexibility must often give way to increased energy efficiency. The limitation in the number and types of communication interfaces may force embedded designers to use inefficient bit-banging techniques to communicate with various modules. Can a co-processor optimized for bit-banging provide this flexibility with an acceptable loss in power efficiency, compared to dedicated hardware modules?
A cycle-accurate instruction set simulator has been developed to support the design of instruction sets and optimization of the bit-banging programs. It is also used to determine the run/sleep ratio for these programs on the individual instruction sets. Complexity based power estimations, that make use of power and complexity measures from an ARM Cortex M0 implementation, are used to estimate the dynamic power consumption of the various instruction sets.
A new set of instructions, called the SOL-instructions, was developed to optimize the output and input of serial data. Together with the addition of the REPEAT-instruction, a 36% reduction in active time was achieved compared to a simple instruction set. Compared to dedicated modules the difference in dynamic power consumption vary with transmission frequency. The power consumption range from 6.7%(UART, 9.6kbps) to 529%(SPI, 1000kbps) of the dedicated hardware's power consumption.
Flexibility is added at the cost of reduced power efficiency for high speed transmissions. The bit-banging processor is perhaps best suited as an addition to existing modules. It can not completely replace dedicated modules for common protocols, but show very promising results as an alternative to bit-banging in the host processor. | |
