Low Power Continuous-Time Delta-Sigma ADC - The robustness of finite amplifier GBW compensation
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This paper reports on the modeling and simulation of a continuous-time delta-sigma analog to digital converter (ADC) in VHDL AMS. The ADC is intended for use in a microcontroller and is therefore underlying restrictions on power consumption. Continuous-time delta-sigma architectures are well known for their good low-power capabilities compared to discrete-time realizations. This is due to their reduced demands to the gain bandwidth product (GBW) of the internal amplifiers in the ADCs. Continuous-time ADCs often operate with GBWs in the range of the sampling frequency, fs. The ADC presented in this work is also employing a previously reported compensation technique which ideally allows the GBW to be reduced further >20 times of this. Considering that the current drain in the amplifiers usually is proportional with GBW, this could be a promising power saving technique. The work focuses on the development of two similar models of a 2-order continuous-time delta-sigma ADC in VHDL-AMS, where one of the ADCs is using the compensation technique. The main purpose is to see how the compensated ADC is affected by nonidealities such as GBW-variation, finite amplifier gain, RC-product variation, excess loop delay and finite DAC slew rate compared to the performance of the noncompensated ADC. The required accuracy for the modeled ADCs is 62dB Signal to Noise and Distortion Ratio (SNDR), thus an appropriate oversampling ratio (OSR) also must be found. The simulations show that the compensated ADC has similar performance as the noncompensated ADC operating with GBW=10*fs when subject to the different nonidealities. With an OSR=64 it stays within the accuracy specification for GBWs >= 0.05*fs This is however only valid if actual GBW stays within +-40% of the GBW compensated for. For larger deviations, especially lower GBW values, the SNDR drops rapidly. It is also shown that the internal signal swing in the ADC is reduced for low GBW values. This may limit the practical achievable SNDR when subject to circuit noise. If these potential drawbacks are circumvented, the compensation technique could lead to a further decrease of the power consumption in continuous-time delta-sigma ADCs.