Gate controlling MPCs as Part of a cascaded MPC Structure, used for harmonic Mitigation in a Ship Power System
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This thesis studies the effect of controlling gate switches in an APF using FCS-MPC. This gave a cascaded MPC structure. Where internal states and a calculated reference from the first MPC is used by a second MPC. The second MPC was designed to track the reference. An FCS-MPC with continuous variables was designed and compared to existing benchmark implementations. Including an ILS-FCS-MPC, an ICS-MPC and a hysteresis controller. The CCV-FCS-MPC was implemented in ACADO. It was based an existing ILS-FCS-MPC. Using an existing model formulation. The cost function was tuned based on theory on Sequantial Quadratic Programmin (SQP). Using a trial and error method to arrive at the final cost function expression. All gate controlling implementations were then verified in a simplified version of the ship power system. Then implemented in the Cascaded MPC structure with the existing harmonic mitigating MPC. First reference tracking performance and power loss was measured. Results show that an CCV-FCS-MPC with a tuned cost function outperforms hysteresis controllers, ICS-MPC with PWM and an existing ILS-FCS-MPC. With a reduction in SSE of at least 50\% compared to any other implementation, while also reducing power loss. Results show that THD in a ship power system is reduced for all MPC implementations, compared to a hysteresis controller. Both for an ICS-MPC, an ILS-FCS-MPC and a CCV-FCS-MPC. The CCV-FCS-MPC with a tuned cost function outperforms all other tested implementations. It reduces generator current THD by over 20\% compared to any other implementation. While also reducing power loss and maintaining bus voltage THD. Compared to the hysteresis controller.