RTL Power Estimation Flow and Its Use in Power Optimization
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The increased complexity and low-power requirements of integrated circuit design demands reliable and accurate power estimations in the RTL phase, for effective design tradeoffs early in the design phase. This thesis develops a methodology to correlate RTL and Netlist power estimations. With a reliable RTL estimation the designer could choose the most power efficient design early in the design phase, leading to a more power efficient IC design. In this work estimations are performed on a set of power scenarios to obtain a power profile of an actual design. The design is synthesized in Synopsys Design Compiler, layout is done in Synopsys IC Compiler, RTL estimation in Spyglass Power and netlist estimation in Primetime PX. For the default design the results yields deviations between RTL and netlist estimation below 5\% for all scenarios. Due to inaccuracy in estimation of analog macros and IO PADs, the analog domain is excluded and only the digital domain is considered for exploration. Several design optimization techniques are implemented in RTL and correlation verified by netlist power estimation. Clock gating is one of the most effective techniques to reduce dynamic power consumption. Both implementation of clock gating cells in the RTL code and automatically interfered clock gates by the synthesis tool is explored for power reduction. By implementing clock gating on a hierarchical level in unused logic, power savings of 82.4 \% is achieved for low activity scenarios. The deviation is within 5\% with the calibration data extracted from the netlist of the default design. Automatic inserted clock gates by the synthesis tool is explored, for a set of bit width threshold values in RTL estimation. The most interesting results is synthesized and verified by netlist power estimation. The netlist estimation shows a power reduction of 41.6\% for low activity scenario and 15\% for high activity scenario, by increasing the bit width to eight bits. The correlation is decreased to 20\% deviation on total power, this inaccuracy needs to be addressed and is left for future work. Much of the dynamic power consumption in integrated circuits comes from high number of transitions on high capacitance buses. Bus encoding schemes aims to minimize the number of transitions to reduce the power consumption. In this work T0 encoding is implemented between the CPU and RAM to reduce the number of transitions. This encoding introduce extra logic with power and area overhead. Since the design used in this thesis is quite small with a low capacitance bus, no power savings is achieved, due to the power overhead. This design was synthesized and performed netlist power estimation which gave deviation below 5.7\%. Sub-threshold leakage in CMOS circuits is becoming increasingly important challenge, since it is dominating more of the total power in smaller process technology nodes. The leakage currents are strongly influenced by the transistor threshold voltage, Vt. One way of reducing the leakage current is to optimize the Vt mix. Exploration of Vt mix is only performed in RTL estimation in this thesis, due to limited time. Netlist estimation demands a more complex place and route to verify timing constraints in all process, temperature and voltage corners. In this work only typical corner is explored, investigating correlation on other corners is left for future work. Extracted calibration data from netlist improves correlation significantly, this thesis show that calibration data from similar designs yields good correlation. This way the methodology can be used by extracting calibration data from a netlist of same technology and similar design to get accurate RTL power estimations without netlist estimations. Achieving reliable power estimation early in the design phase. The methodology describes how accurate RTL power estimations could be achieved by isolating the design to only the digital domain, and thorough debugging of the power numbers against a gate level reference.