Turbo Amber: A high-performance processor core for SHMAC

Abstract

The performance increase of state of the art processors has stagnated dueto power and thermal constraints. Heterogeneous computing has latelyattracted interest and may be the key for improving the performanceand energy-efficiency of computing systems under their tight physicalbudgets. The Single-ISA Heterogeneous MAny-core Computer (SHMAC)project is a research project that seeks to explore the challenges ofheterogeneous computing. Therefore, the SHMAC project requires adiversity of processor cores of different size and performance, to exploreheterogeneous architectures.Currently, there is only one processor core, Amber, available for SHMAC.This thesis presents the development of Turbo Amber (TA), a high-performance processor core for SHMAC. We present an overview of high-performance processor architecture techniques and extend the existingAmber core with a branch predictor, a return address stack, an instructionqueue and a fast multiplier. The front-end of TA is capable of fetchingand performing branch prediction on up to four instructions each clockcycle and can be extended with an appropriate back-end for superscalarexecution.Our results show that TA has a performance increase of 49% over theoriginal Amber core, with a moderate increase in FPGA resource utiliza-tion: slice utilization from 4.7% to 7.9%, block RAM utilization from1.0% to 3.3%, and no DSP slices used on a Xilinx Virtex-5 FPGA. TAhas also been integrated into the existing SHMAC-infrastructure andverified by running applications on top of Linux and freeRTOS.