Managing Shared Resources in Chip Multiprocessor Memory Systems

Abstract

Chip Multiprocessors (CMPs) have become the architecture of choice for high-performance general-purpose processors. CMPs often share memory system units between processes. This may result in independent processes competing for memory bandwidth. Such competition can cause destructive interference which reduces performance predictability, decreases operating system scheduler effciency and complicates billing for cloud computing providers.

In this thesis, we reduce the eects of these problems by managing miss band-width. We use dynamic interference feedback to choose the number of Miss Information/Status Holding Registers (MSHRs) available in last-level private cache of each processor. Furthermore, we provide two dierent allocation approaches that use this mechanism to improve system performance. The rst approach uses simple measurements to decide miss bandwidth allocations and performance feedback to determine if the allocations are bene cial. The second approach selects its allocations based on a miss bandwidth performance model. This model leverages a novel interference measurement scheme called the Dynamic Interference Estimation Framework (DIEF). DIEF provides accurate estimates of the average memory latency a process would experience with exclusive access to all hardware-managed shared resources.

We also investigate the eects of managing memory bandwidth to increase memory bus utilization. Here, we choose prefetches to effciently utilize the complex DRAM structure of banks, rows and columns. This policy makes prefetches cheaper than demand accesses and increases the performance of processes with predictable access patterns. In addition, effcient prefetch scheduling reduces the degree to which prefetches interfere with the demand accesses of other processes.